Analog Devices Inc. AD9986 4T2R RF Transmitter & Observation Receiver
Analog Devices Inc. AD9986 4T2R Direct RF Transmitter and Observation Receiver is a highly integrated device with a 16-bit, 12GSPS maximum sample rate RF DAC core and a 12-bit, 6GSPS rate RF ADC core. The AD9986 offers four transmitter channels and two receiver channels with four transmitters, two receivers (4T2R) configurations.
The ADI AD9986 4T2R Direct RF Transmitter and Observation Receiver is designed for 2-antenna and 4-antenna transmitter applications requiring a wide bandwidth observation receiver path for the digital predistortion. The AD9986 provides up to a 6GSPS complex transmit and receive data rate in single-channel mode. The device supports a maximum radio channel bandwidth of 1.2GHz and 2.4GHz for the transmit and receive paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75Gbps JESD204C or 15.5Gbps JESD204B serial data port, an on-chip clock multiplier, and digital signal processing. These capabilities are targeted at multiband, direct-to-RF radio applications.
The AD9986 RF Transmitter and Observation Receiver is available in a 15mm × 15mm, 324-ball BGA with 0.8mm pitch.
Features
- Flexible reconfigurable radio common platform design
- Transmit/receive channel bandwidth up to 1.2GHz/2.4GHz (4T2R)
- RFDAC/RFADC RF frequency range up to 7.5GHz
- On-chip PLL with multichip synchronization
- External RFCLK input option
- Versatile digital features
- Configurable digital up/down conversion (DDC and DUC)
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent
- 48-bit NCO per DUC/DDC
- Configurable digital up/down conversion (DDC and DUC)
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Dedicated AGC support pins
- Transmit DPD support
- Programmable delay and gain per transmit data path
- Coarse DDC delay adjust for DPD observation path
- Auxiliary features
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Programmable GPIO pins supporting different user configurations
- ADC clock driver with selectable divide ratios
- TDD power savings option and sharing ADCs
- SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75Gbps
- 8 lanes per each DAC and ADC
- JESD204B is compatible with a maximum 15.5Gbps lane rate
- JESD204C is compatible with a maximum 24.75Gbps lane rate
- Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit)
- 15mm × 15mm, 324-ball BGA with 0.8mm pitch
Applications
- Wireless communications infrastructure
- W-CDMA, LTE, LTE-A, Massive-MIMO
- Microwave point-to-point, E-band, and 5G mm Wave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Communications test and measurement system
Associated Eval Board
Analog Devices Inc. EVAL-AD9986 Evaluation Board
Provides all of the support circuitry required to operate the AD9986 in any mode & configuration.
Block Diagram
