SN74HC166PWG4

SN74HC166 8-Bit Parallel-Load Shift Registers

Texas Instruments SN74HC166 8-Bit Parallel-Load Shift Registers feature gated clock inputs (CLK, CLK INH) and an overriding clear (CLR) input. The shift/load (SH/LD) input establishes the parallel-in or serial-in modes. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. Serial data flow is inhibited during parallel loading. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate. This feature permits one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This feature allows the system clock to run freely, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. The CLR on the Texas Instruments SN74HC166 overrides all other inputs, including CLK, and resets all flip-flops to zero.